In a data processing system, multiple computation threads may share a common data resource such as a memory. Copies of a data value associated with a memory address may be stored at different locations in the data processing system, such as caches. In such systems, a coherence mechanism may be used to monitor the current status and ensure that out of date data value are not used.
In some situations, a single thread may require data at a set of memory addresses not be changed by any other thread while a sequence of operations is performed. This sequence of operations is referred to as a ‘transaction’. The transaction is said to have ‘multi-threaded atomicity’, in that the memory accesses appear to have happened in a single operation that cannot be split by other threads. One way to ensure that memory is not changed by other threads is to block access to the memory by all other threads. However, this is not efficient, since threads that access memory addresses outside of the restricted set of addresses will be blocked unnecessarily. Another approach is to buffer write operations in a ‘redo log’ until the operation is complete and then write all of the data in a single operation provided no other thread has accessed the restricted memory. This is sometimes called a ‘lazy’ approach. A further approach is to perform the write operations, but to record the overwritten values in an ‘undo’ log. The write operation can then be undone if any other thread has accessed the restricted memory. This is sometimes called a ‘eager’ approach.
In above approaches, logs may be maintained in volatile or persistent (non-volatile) memory. However, neither each approach is optimal. If the logs are maintained in volatile memory they will be lost in the event of a power failure and the memory may be corrupted. If the logs are maintained in a non-volatile memory, memory accesses within the transaction will be redirected to the non-volatile memory, which is typically much slower than a volatile memory such as a cache. This will slow down execution.
There exists a need for a transactional memory system that maintains efficiency and yet is robust in the presence of a power failure.